Table of Contents
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Table of Contents
Front Panel for Z80
Introduction
The front panel enters data into Z80 via PS2 keyboard, run/single-step Z80, and display address/data on 7-segment display. Discussion about the front panel can be found here.
Features
Front panel controller for Z80
EPM7128S based logic
Data entry via PS2 keyboard
Four 7-segment display for address and two 7-segment display for data
Data entry mode
Run/Single step mode
RC2014 compatible
Theory of Operation
The purpose of the front panel is to control a Z80 computer use PS2 keyboard and display results via six 7-segment displays. It has two modes of operation, data entry and run/single-step modes. The 'Esc' key toggles between data entry mode and run/single-step mode. These features are implemented in CPLD state machines:
* After reset Z80 is bus master in run/single step mode. While in this mode keyboard input 'S' single-step Z80; keyboard input 'R' toggles Z80 between continuous run or single step. Keyboard input 'Esc' asserts Z80 nBUSREQ and the front panel state machine takes over Z80 bus after current cycle is completed. 'Esc' toggles bus mastership between Z80 and Front Panel State Machine.
* In data entry mode the Front Panel State Machine is the bus master; keyboard input 'Space' set the address field to 0x0 and read/display memory value of 0x0; keyboard input 'Enter' writes displayed data value to current address location, advances address by 1, then display the memory content of address+1; keyboard input 'Backspace' decreases address by one then display the memory content of address-1. Keyboard input '0' to '9', 'a' to 'f' changes the memory content of current address. Data value is not written to memory until 'Enter“ is pressed. Keyboard input 'X' redirects next 4 keystrokes to edit the 4-digit address field; after the 4th keystroke, the memory content of newly entered address is read and displayed and subsequent keystrokes will only affect the data field until next 'X' key is entered.
Front Panel Design files
Prototype schematic
CPLD Design info
Top level CPLD schematic
CPLD design files