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VGA Piggybacked on RAM, An Experimental Prototype
Introduction
The design of a simple VGA using dual port RAM and CPLD was discussed here. Posts after May 25, 2021 described an experimental prototype where the dual port RAM, CPLD, and oscillator are glued on top of a 128KB RAM such that the content of a portion of the RAM is displayed as 64-column X 48-line text. This page describes the detailed design of this experimental prototype. A pc board version of the piggybacked VGA prototype is here.
Features
Add VGA function to existing system RAM
128KB RAM
4K dual port RAM
64-macrocell CPLD, EPM7064SLC44
Each character is 8×8 pixels
25.175MHz oscillator
HD15 VGA connector
Theory of Operation
The VGA circuit consists of a 4KB dual port RAM, CPLD, and 25.175MHz oscillator. One side of the dual port RAM snoops a 4KB space of the system RAM such that every write to the 4KB space modifies both system RAM as well as the dual port RAM while a read only return the content of the system RAM. The other side of the dual port RAM is controlled by the CPLD state machine where the first 3KB contains the text memory and are read sequentially and continuously into CPLD. The text value is used to look up corresponding entry in the font table located at the top 1KB of the dual port RAM. The bit patterns from the font table is loaded into a shift register and output to RGB outputs at 25.175MHz pixel rate.
Design Files
Schematic of the CPLD design
test file to be loaded into 0xA000-0xAFFF and generates the text screen of above picture
Prototype assembly blog
