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Table of Contents
6502 Coprocessor using Dual Port RAM
Introduction
This design is very similar to Z80 version of Z80 coprocessor with dual port RAM. See on-line discussion here.
Features
4K dual port RAM
64-macrocell EPM7064S CPLD
W65C02 processor
Prototype area
RC6502 bus interface
Theory of Operation
The basic idea is two 6502 sharing a 4K dual port RAM. The main 6502 processor set aside 4K RAM space for the dual port RAM, but the coprocessor only has 4K for program and data. an under-utilized CPLD provides the glue logic between these two processors. There are plenty of logic left in the CPLD to add more features, whatever those may be.
At reset the coprocessor is in reset waiting main processor to write to a magic location to release the reset. The 4K dual port RAM is mapped to both coprocessor's top 4K (reset, interrupt, NMI vectors) as well as the bottom 4K (zero page, stack). The main processor first writes reset vector, interrupt vectors to top of 4K and whatever application program; write to a magic location to release the reset; and communicate to coprocessor via dual port RAM and interrupts.
The board is not standalone; it is meant to plug into a RC6502 style connector as shown in the picture.
Design Information
Projects
128x64 OLED display
Using the coprocessor to bit-bang I2C bus driving a 128×64 OLED display.
