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Table of Contents
Dual Port RAM Prototype Board for RC2014
Introduction
DPRAM prototype board is for exploration of multiprocessor on RC2014. The key component is IDT7134 4K dual port RAM that's accessible to RC2014 as 4K of I/O space. A Z80 slave processor and a CPLD complete the prototype board. There are good bit of discussions about this board on Google Forum retro-comp.
Features
IDT71342 4K dual port RAM with hardware semaphores
Z80 coprocessor.
EPM7064S CPLD as glue logic
RC2014 bus interface
Prototype area
Theory of Operation
IDT7134 is accessible to the main Z80 as 4K of contiguous I/O space using the “in a,( c )” and “out ( c ),a” instructions where reg pair BC points to the I/O address. The other memory port is mapped to 0x0-0x3FFF memory space of the Z80 coprocessor. On reset, Z80 coprocessor is held in reset while the dual port RAM is loaded with appropriate instructions and data. Once instruction is loaded, Z80 coprocessor is released to run. The coprocessor and main processor can communicate asynchronously over the dual port RAM. In fact, the coprocessor and main processor can be different CPU running different clocks.
Design Information
CPLD design ← this is CPLD template with correct pin assignments. DPRAM base address is 0x40; release Z80 reset by writing to I/O 0xF4.
Design Examples
Testing a newly assembled DPRAM board
Program the CPLD with the CPLD template.
load DPRAM_tst and run from 0x1000. Read I/O port 0x40; the value should be changing constantly.
Game of Life accelerator
Conway's game of life running on 128×64 OLED display requires significant computation power. In this design example, the coprocessor drives the OLED display while the main processor and another coprocessor provides the data.
Schematic
Engineering change
Sound Coprocessor
Z80 coprocessor drive the YM2149 sound chip, freeing up the main processor for other tasks.
High-speed Serial Ports Coprocessor
Z80 coprocessor interface with the quad-serial ports which is capable of multi-megabit transfer on each serial channel.
