/* Imported from Wayback Machine
Original URL : https://retrobrewcomputers.org/doku.php?id=boards:sbc:sbc_v2:sbc_v2-005:development Snapshot date: 2021-04-14 Generator : wayback-archiver
*/
Updated design to include the following changes:
1Mb Flash memory implemented with 2 x 512Kb Flash chips.
Dual boot ROMWBW BIOS support option.
Expanded ROM disk option.
Development of read/write Flash filesystem in ROMWBW
In this development, legacy support of DIP style EPROMs and Flash chips are sacrificed for improved Flash ROM capacity. PLCC-32 style Flash chips such as the 39SF040 provide the footprint spaces saving required to mount two 512Kb chips.
Status:
Prototype working.
Board routed.
Writing 1024k rom file works.
Board constructed.
Testing …
Complete
To do:
Test design change and prototype.
005a - Prototype did not work. Monitor CS lines identified ROM select logic does not work, so back to the drawing board.
005b - Chip select logic updated. Requires additional OR gate which is unavailable. and so is implemented using discrete components.
005c - Reworked chip select logic to eliminate discrete OR gate. Added 1K pullups for improved reliability.
005f - Change recovery jumper to switch.
Finalize and release design.
Speed test.
4Mhz works.
10Mhz flakey works.
Running daily with 12Mhz.
Speeds as fast as 20Mhz reported working with F and AHCT parts and 55ns RAM/ROM YMMV.
Complete.
* Developing Flash4 update to support 1Mb write.
Patch developed. Withdrawn, did not work. Documentation below updated.
Flash4 Version 1.3.4 working – now in ROMWBW development build.
Complete.
Test AT49F040 compatibility
DIP32 chips received.
PLCC32 chips ordered.
Both 39SF040 and 49F040 PLCC chips work with Flash4 1.3.4 and version 005c board
Complete.
Developing BIOS Flash routines.
Chip ID working.
Chip erase working.
Sector erase working.
Sector write working.
Sector read working.
Reading/writing to/from low memory now working,
Flash routines integrated into memory disk drivers.
Verify after write added.
Testing and optimizing prior to release.
Complete
Develop bootrom flash utility for update or recovery.
Beta version submitted to ROMWBW development build.
Complete
Dual boot ROMWBW BIOS support option.
Canceled proposal to install jumpers to be able to boot from Flash #2.
Utilize Xmodem Flash Updater to Flash to Flash #2
Duplicate function added to create backup of current Flash.
Complete.
The following routines have been developed to access 39SF040 Flash devices in the ROMWBW environment:
Identify Flash Chip
Erase Flash Sector
Read Flash Sector
Verify Flash Sector
Write Flash Sector
These are relocatable routines as they must be executed from the high memory area (>8000h) as Flash and RAM is switched in and out of the low memory area (<8000h).
When these routines are required to be access by BIOS drivers, individual routines are copied to a high memory buffer before execution on an as needed basis.
When the routines are being used by an application then all routines can be relocated to high memory and remain there.
The SBC-V2 already supports up to 1Mb of EPROM. However, the maximum DIP-32 style Flash device is 512Kb as Flash requires a write pin, so it has one less address line.
Two chip select signals need to be developed to cater for the change from a 1Mb device to 2x512Kb devices This is achieved using the existing chip select signal /CS_ROM and the A19 address line.
When /CS_ROM is active (low), A19 determines which chip is selected. The required logic table is:
/CS_ROM A19 /CS_ROM1 /CS_ROM2 1 1 1 1 1 0 1 1 0 1 1 0 0 0 0 1
Note that when /CS_ROM is high, neither flash chip is active.
The ideal logic elements to develop these signals are shown in Figure 1 below. However, the SBC-V2 does not have a spare OR gate so a discrete component OR gate was implemented initially. This required adding two diodes and a resistor to the board layout.
An OR gate can also be replaced by a NAND gate with both inputs inverted as shown in Figure 2. However, the SBC-V2 only has two spare inverters.
The final design is implemented in Figure 3 which uses the remaining spare components on the SBC-V2 board.