/* Imported from Wayback Machine
   Original URL : https://retrobrewcomputers.org/doku.php?id=builderpages:plasmo:vgarc:ps2ec
   Snapshot date: 2022-05-26
   Generator    : wayback-archiver
*/

==== Table of Contents ====

[[#engineering_change_for_adding_ps2_interface_to_vgarc_rev01|Engineering Change for adding PS2 interface to VGARC rev0.1]]

[[#introduction|Introduction]]

[[#board_modifications|Board modifications]]

[[#connections_to_ps2_connector|Connections to PS2 connector]]

[[#connections_to_data_bus|Connections to Data bus]]

[[#cpld_changes|CPLD Changes]]

[[#test_software|Test Software]]

====== Engineering Change for adding PS2 interface to VGARC rev0.1 ======

===== Introduction =====

This engineering change describe the pc board modifications, CPLD design changes, and software required for adding PS2 interface to VGARC rev0.1

===== Board modifications =====

To enable PS2 interface, test points T3 and T4 are connected to PS2 connector Data and Clock. Test points T5, T6, T7 are connected to data bus D[0], D[1], D[7].

==== Connections to PS2 connector ====

+5V (silkscreen '+') is connected to PS2 connector pin 4

Ground (silkscreen '-') is connected to PS2 connector pin 3

T3 is pulled up through a 4.7K resistor to +5V and connected to PS2 connector pin 1

T4 is pulled up through a 4.7K resistor to +5V and connected to PS2 connector pin 5

==== Connections to Data bus ====

T5 is connected to data bus D[0] (RC2014 connector pin 27)

T6 is connected to data bus D[1] (RC2014 connector pin 28)

T7 is connected to data bus D[7] (RC2014 connector pin 34)

[[https://www.retrobrewcomputers.org/lib/exe/fetch.php?tok=03797f&media=https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/builderpages/plasmo/vgarc/dsc_61661129.jpg|{{https://retrobrewcomputers.org/lib/exe/fetch.php?w=600&h=400&tok=0cb8c7&media=https%3A%2F%2Fwww.retrobrewcomputers.org%2Flib%2Fplugins%2Fckgedit%2Ffckeditor%2Fuserfiles%2Fimage%2Fbuilderpages%2Fplasmo%2Fvgarc%2Fdsc_61661129.jpg?600x400|www.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_builderpages_plasmo_vgarc_dsc_61661129.jpg}}]]

[[https://www.retrobrewcomputers.org/lib/exe/fetch.php?tok=706e24&media=https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/builderpages/plasmo/vgarc/dsc_61651129.jpg|{{https://retrobrewcomputers.org/lib/exe/fetch.php?w=600&h=400&tok=554404&media=https%3A%2F%2Fwww.retrobrewcomputers.org%2Flib%2Fplugins%2Fckgedit%2Ffckeditor%2Fuserfiles%2Fimage%2Fbuilderpages%2Fplasmo%2Fvgarc%2Fdsc_61651129.jpg?600x400|www.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_builderpages_plasmo_vgarc_dsc_61651129.jpg}}]]

[[https://www.retrobrewcomputers.org/lib/exe/fetch.php?tok=613bf2&media=https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/builderpages/plasmo/vgarc/dsc_61671129.jpg|{{https://retrobrewcomputers.org/lib/exe/fetch.php?w=500&h=263&tok=c762c4&media=https%3A%2F%2Fwww.retrobrewcomputers.org%2Flib%2Fplugins%2Fckgedit%2Ffckeditor%2Fuserfiles%2Fimage%2Fbuilderpages%2Fplasmo%2Fvgarc%2Fdsc_61671129.jpg?500x263|www.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_builderpages_plasmo_vgarc_dsc_61671129.jpg}}]]

===== CPLD Changes =====

[[https://retrobrewcomputers.org/lib/exe/fetch.php?media=builderpages:plasmo:vgarc:vga56x80_ps2_keyboard.zip|Here]] is the CPLD design file for VGARC with PS2 interface.

Schematic of the [[https://retrobrewcomputers.org/lib/exe/fetch.php?media=builderpages:plasmo:vgarc:ps2_interface.pdf|PS2 interface]].

PS2 keyboard is access via bit banging I/O address 0xF4. There are 3 data bits on 0xF4 associated with PS2 keyboard. D[0] is PS2 Data, D[1] is PS2 enable, and D[7] is PS2 clock. At reset D[0] and D[7] are set to 1 (idle) while D[1] is set to low (disabled).

I/O address 0xF4 is readable and writable. Write only affect states of bit D[0], D[1], and D[7] while read captures the state of PS2 Data and PS2 Clock lines on D[0] and D[7], respectively. The keyboard interface is disabled at reset or by writing '0' to D[1] of the PS2 keyboard register. While disabled, PS2 Data and Clock are floating pulling up by 4.7K pull-up resistors. Writing '1' to D[1] of the PS2 keyboard register enables PS2 interface so the register contents of D[0] and D[7] are driven to PS2Data and PS2Clock, respectively.

===== Test Software =====