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| builderpages:plasmo:zrcc:zrcc1:mem_map_zrcc1 [2024/11/10 15:17] – Revision from 2024-11-10 | builderpages:plasmo:zrcc:zrcc1:mem_map_zrcc1 [2026/06/15 13:17] (current) – external edit 127.0.0.1 | ||
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| + | /* Imported from Wayback Machine | ||
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| + | */ | ||
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| + | ====== ZRCC Memory, I/O map ====== | ||
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| + | ===== Memory Map ===== | ||
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| + | The memory is consists of 128K of RAM in four 32-K banks: | ||
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| + | Top 32K of RAM is the common memory. The bottom 32K can be bank selected by writing to bank select register at I/O location 0x1F as follow: | ||
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| + | 0x0 is normal operation. This is the reset value | ||
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| + | 0x1 available, no specific assignment | ||
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| + | 0x2 is for bank 0 of CP/M-3 | ||
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| + | 0x3 is the top 32K of physical memory. This is the common memory that should not map to the lower 32K in normal operation. | ||
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| + | ===== I/O Map ===== | ||
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| + | ==== UART ==== | ||
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| + | A hardware receiver is implemented in CPLD with the following I/O addresses: | ||
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| + | Read-only serial data receive register at 0xF9 | ||
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| + | Read-only serial receive status register at 0xF8 where | ||
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| + | D[0] is the receive ready flag, 1 indicates data is ready, 0 indicates no data | ||
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| + | Write-only bit-bang transmit register at 0xF9 | ||
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| + | The content of D[0] appears on the TX output pin. D[0] is high at reset. Software must “bit-bang” D[0] of transmit register to emulate the serial port transmit function. | ||
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| + | ==== Compact Flash Registers ==== | ||
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| + | Compact flash registers are 0x10 to 0x17 | ||
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| + | ==== Bank Select Register ==== | ||
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| + | Bank select register is write only located at 0x1F. Reset value of bank select register is 0x0 | ||
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| + | bit 0 controls RAM address 15 | ||
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| + | bit 1 controls RAM address 16 | ||
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| + | bit 3 controls LED and jumper pad T4 | ||
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| + | bit 4 controls 64 byte ROM page. When low (the reset value), the first 64 bytes of memory, 0x0-0x3F are mapped to CPLD internal ROM. When high, all memory are mapped to RAM. Once bit 4 is set high and internal ROM is disabled, it will remain high until next reset. | ||
