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| builderpages:plasmo:tinyz280 [2025/05/16 01:45] – Revision from 2025-05-16 | builderpages:plasmo:tinyz280 [2026/06/15 13:14] (current) – external edit 127.0.0.1 | ||
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| /* Imported from Wayback Machine | /* Imported from Wayback Machine | ||
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| */ | */ | ||
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| ===== Design Concept ===== | ===== Design Concept ===== | ||
| - | [[https://www.retrobrewcomputers.org/ | + | [[https:// |
| UART bootstrap. This method is based on Z280's UART bootstrap feature where nWAIT signal is asserted and the value 0x40 is presented on the data bus AD[7:0] when nRESET signal is negated. This will cause Z280 to enter its UART bootstrap mode where it will configure DMA channel 0 to transfer 256 bytes of data from UART to memory location 0-0xFF. Once 256 bytes of data are received, it will release the reset to Z280 CPU and program execution will start at location 0. The serial baud rate is determined by the clock to counter channel 1 divided by 16. The parity is set to odd. The current serial configuration is 57600, odd parity, 8 data bits, 1 stop. This configuration requires either SIMM DRAM or two 128Kx8 RAM in U3 and U4 | UART bootstrap. This method is based on Z280's UART bootstrap feature where nWAIT signal is asserted and the value 0x40 is presented on the data bus AD[7:0] when nRESET signal is negated. This will cause Z280 to enter its UART bootstrap mode where it will configure DMA channel 0 to transfer 256 bytes of data from UART to memory location 0-0xFF. Once 256 bytes of data are received, it will release the reset to Z280 CPU and program execution will start at location 0. The serial baud rate is determined by the clock to counter channel 1 divided by 16. The parity is set to odd. The current serial configuration is 57600, odd parity, 8 data bits, 1 stop. This configuration requires either SIMM DRAM or two 128Kx8 RAM in U3 and U4 | ||
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| [[https:// | [[https:// | ||
| - | PC board design files are [[https://www.retrobrewcomputers.org/ | + | PC board design files are [[https:// |
| Construction notes is [[builderpages: | Construction notes is [[builderpages: | ||
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| The picture above shows what need to be populated to support the UART bootstrap configuration. The serial port is set to 57600 baud, odd parity, 8 data bit, 1 stop. The operating guide for UART Bootstrap configuration is [[builderpages: | The picture above shows what need to be populated to support the UART bootstrap configuration. The serial port is set to 57600 baud, odd parity, 8 data bit, 1 stop. The operating guide for UART Bootstrap configuration is [[builderpages: | ||
| - | The Altera EPM7128 design for UART bootstrap is [[https://www.retrobrewcomputers.org/ | + | The Altera EPM7128 design for UART bootstrap is [[https:// |
| When reset button is pressed or when initially powered up, the board expects a 256-byte serial binary data stream. After 256 bytes of data is received, Z280 will start program execution at location 0. TinyLoad is the 256-byte boot program; it has three functions: | When reset button is pressed or when initially powered up, the board expects a 256-byte serial binary data stream. After 256 bytes of data is received, Z280 will start program execution at location 0. TinyLoad is the 256-byte boot program; it has three functions: | ||
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| </ | </ | ||
| - | TinyLoad binary is [[https://www.retrobrewcomputers.org/ | + | TinyLoad binary is [[https:// |
| Glitchmon is a small monitor that display/ | Glitchmon is a small monitor that display/ | ||
| - | Glitchmon hex load file is [[https://www.retrobrewcomputers.org/ | + | Glitchmon hex load file is [[https:// |
| cpm22all is CP/M ver 2.2 source in Z80 mnemonics. The CCP and BDOS are downloaded from cpm.z80.de: http:// | cpm22all is CP/M ver 2.2 source in Z80 mnemonics. The CCP and BDOS are downloaded from cpm.z80.de: http:// | ||
| - | cpm22all hex load file is [[https://www.retrobrewcomputers.org/ | + | cpm22all hex load file is [[https:// |
| ==== Step 2, CF Bootstrap ==== | ==== Step 2, CF Bootstrap ==== | ||
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| (2/11/18) CF Bootstrap is working. The pc board is modified to add a jumper that switch between UART bootstrap and CF bootstrap. The reset connection (T14 & T15) is cut and a new output signal from CPLD is now control the reset of the Z280. This is all the physical modifications required. There are significant more firmware and software changes: | (2/11/18) CF Bootstrap is working. The pc board is modified to add a jumper that switch between UART bootstrap and CF bootstrap. The reset connection (T14 & T15) is cut and a new output signal from CPLD is now control the reset of the Z280. This is all the physical modifications required. There are significant more firmware and software changes: | ||
| - | New CPLD with CF bootstrap state machine (CFinit) and modified memory map. Here is the[[https:// | + | New CPLD with CF bootstrap state machine (CFinit) and modified memory map. Here is the[[https:// |
| - | CF Bootstrap software is evolving. The current approach is a small (~128 byte) cold bootstrap code located in boot sector of a CF. Before Z280 reset is released, the CFinit state machine configured the CF to stream cold bootstrap code out to CF's 16-bit data port. After reset Z280 will execute the code stream which copy a small boot loader into 0x1000 and jump to it which, in turn, load data from sector 2 and 3 and execute. Here is the[[https:// | + | CF Bootstrap software is evolving. The current approach is a small (~128 byte) cold bootstrap code located in boot sector of a CF. Before Z280 reset is released, the CFinit state machine configured the CF to stream cold bootstrap code out to CF's 16-bit data port. After reset Z280 will execute the code stream which copy a small boot loader into 0x1000 and jump to it which, in turn, load data from sector 2 and 3 and execute. Here is the[[https:// |
| ==== Step 3, CF Bootstrap with DRAM ==== | ==== Step 3, CF Bootstrap with DRAM ==== | ||
