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--- builderpages:plasmo:frr512k:rev0:emul6850 [2023/01/31 07:07] – Initial import from Wayback Machine
+++ builderpages:plasmo:frr512k:rev0:emul6850 [2026/06/15 12:02] (current) – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
+/* Imported from Wayback Machine
+   Original URL : https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:frr512k:rev0:emul6850
+   Snapshot date: 2023-01-31
+   Generator    : wayback-archiver
+*/
+====== Partial Emulation of MC6850 ACIA ======
+===== Introduction =====
+When using the ACIA in the popular no-parity, 8-data, and 1 stop bit mode and when baud clock is integer multiple of system clock, the ACIA design simplifies significantly so it can be emulated with a small CPLD. This repurposed FRR512K board describes such emulation.
+[[https://www.retrobrewcomputers.org/lib/exe/fetch.php?tok=2ec2ab&media=https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/builderpages/plasmo/frr512k/rev0/dsc_65850611.jpg|{{https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/builderpages/plasmo/frr512k/rev0/dsc_65850611.jpg?600x360|www.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_builderpages_plasmo_frr512k_rev0_dsc_65850611.jpg}}]]
+[[https://www.retrobrewcomputers.org/lib/exe/fetch.php?tok=ec5eec&media=https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/builderpages/plasmo/frr512k/rev0/dsc_65860611.jpg|{{https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/builderpages/plasmo/frr512k/rev0/dsc_65860611.jpg?500x311|www.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_builderpages_plasmo_frr512k_rev0_dsc_65860611.jpg}}]]
+===== Features =====
+Serial port setting of 115200, 8-data, 1-stop, and no parity
+Serial baud must be integer multiple of system clock
+Implemented in EPM7064SLC44
+Re-purposed FRR512K board
+===== Design Information =====
+[[https://www.retrobrewcomputers.org/lib/exe/fetch.php?media=builderpages:plasmo:frr512k:rev0:6850_emulate_frr512krev0.zip|CPLD design file]]
+[[https://www.retrobrewcomputers.org/lib/exe/fetch.php?media=builderpages:plasmo:frr512k:rev0:emulated_6850_cpld_scm.pdf|PDF schematic]] of the CPLD design file
+==== Engineering change ====
+=== Interrupt ===
+Flash-pin30 (Bank3) to T7 (nINT)
+=== Serial Connections ===
+SCL to serial hdr pin2 (TxD)
+SDA to serial hdr pin3(RxD)
+serial hdr pin5 to GND
+serial hdr pin1 (nRTS) to flash-pin22(nROMCS)
+=== Data bus connections ===
+Flash-pin1 (Bank4) to Flash-pin 18 (D4)
+Flash-pin2 (Bank2) to Flash-pin19(D5)
+Flash-pin3(Bank1) to Flash-pin20(D6)
+=== Components Populated ===
+P1, RC2014 bus connector,
+U1, EPM7064SLC44
+P3, CPLD programming header
+P21, 6-pin serial port header
+U2, Oscillator
+R1,R4, 4.7K resistors
+ohm resistor between T8 and T37
+Bypass capacitors