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| builderpages:plasmo:eazy80:rev0pcb:rev0pcbec [2025/12/08 16:19] – Initial import from Wayback Machine | builderpages:plasmo:eazy80:rev0pcb:rev0pcbec [2026/06/15 12:01] (current) – external edit 127.0.0.1 | ||
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| + | /* Imported from Wayback Machine | ||
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| + | */ | ||
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| + | ====== Engineering Changes for Rev0 PCB of EaZy80 ====== | ||
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| + | Link to [[https:// | ||
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| + | Link to [[https:// | ||
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| + | ===== Description ===== | ||
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| + | Controlling two banks of 64K RAM: cut ground trace on component side connecting to pin 2 of U3 (RAM); solder a 4.7K resistor from pin 2 of U3 to ground; connect pin 2 U3 to pin 11 U4 (KIO) | ||
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| + | Controlling RAM output enable: connect U3 pin 24 to U4 pin 30 | ||
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| + | Second serial port handshake: connect P2 pin 1 to U4 (KIO) pin29. | ||
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| + | Console serial port handshake: connect P3 pin 1 to U4 pin 14 | ||
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| + | Serial ports clock source: connect U3-56 to U3-73 to U3-16 to U3-4 | ||
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| + | Enable console handshake: connect U3-8 (/DCDA) to ground, pull U3-9 (/CTSA) to ground through a 1K resistor. | ||
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| + | Enable 2nd serial port handshake: connect U3-7 (/DCDB) to ground, pull U3-6 (/CTSB) to ground through a 1K resistor. | ||
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| + | Enable DMA: pull U3-45 (ARDY) and U3-46 (/ASTB) to VCC through a 4.7K resistor. | ||
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| + | [[https:// | ||
