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--- builderpages:plasmo:cb030:cb030_rev1:cb030r1_memmap [2025/02/14 07:25] – Revision from 2025-02-14
+++ builderpages:plasmo:cb030:cb030_rev1:cb030r1_memmap [2026/06/15 13:05] (current) – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
+/* Imported from Wayback Machine
+   Original URL : https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:cb030:cb030_rev1:cb030r1_memmap
+   Snapshot date: 2025-02-02
+   Generator    : wayback-archiver
+*/
+====== CB030 Rev 1 Memory Map ======
+The memory map of CB030 (rev1) at reset is as follow:
+EPROM from 0x0 to 0xFEFF_FFFF, the EPROM is 512K (0x0-0x7FFFF), the memory is aliased every 512K up to 0xFEFF_FFFF.
+I/O resources is at 0xFF00_0000 to 0xFFFF_FFFF
+address is 0xFFFF_F000-0xFFFF_FFFF
+Compact flash interface is 0xFFFF_E000-0xFFFF_EFFF
+RC2014-like expansion slot is from 0xFFFF_C000-0xFFFF_CFFF for I/O addresses (nIORQ signal asserted), 0xFFFF_D000 to 0xFFFF_DFFF for memory addresses (nMREQ signal asserted).
+Remap register is 0xFFFF_8000-0xFFFF_8FFF, any access (read or write) to 0xFFFF_8000 will cause EPROM to reside in 0xFE00_0000 to 0xFEFF_FFFF
+(rev1.2 version of CPLD) 100Hz level 2 autovector interrupt turned on by accessing 0xFFFF_9800. Turn off the 100Hz timer by accessing 0xFFFF_9000
+Once the remap register is access, the memory map is changed to:
+RAM from 0x0 to 0x7FF_FFFF. If the DRAM is single bank 16 meg DRAM, it is located at 0x0-0x100_0000 and aliased three time to 0x3FF_FFFF. If the DRAM is 64 meg, then it is located at 0x0-0x3FF_FFFF. If the DRAM is 128meg it is located from 0x0-0x7FF_FFFF.
+EPROM from 0xFE00_0000 to 0xFEFF_FFFF, the EPROM is 512K, the memory is aliased every 512K up to 0xFEFF_FFFF.
+I/O from 0xFFFF_0000 to top of memory
+address is 0xFFFF_F000-0xFFFF_FFFF
+Compact flash interface is 0xFFFF_E000-0xFFFF_EFFF
+RC2014-like expansion slot is from 0xFFFF_C000-0xFFFF_CFFF for I/O addresses (nIORQ signal asserted), 0xFFFF_D000 to 0xFFFF_DFFF for memory addresses (nMREQ signal asserted).
+Remap register is 0xFFFF_8000-0xFFFF_8FFF, any access (read or write) to 0xFFFF_8000 will cause EPROM to reside in 0xFE00_0000 to 0xFEFF_FFFF.
+EQU template for 68681
+<code code>
+DUART    equ $FFFFF000    * base address of 68692 DUART
+MRA    equ $FFFFF000    * mode reg A
+SRA    equ $FFFFF002    * status A (read)
+CSRA    equ $FFFFF002    * clock select reg (write)
+CRA    equ $FFFFF004    * command register (write only)
+RHRA    equ $FFFFF006    * Rx Hold reg A (read)
+THRA    equ $FFFFF006    * Tx Holding reg (write)
+IPCR    equ $FFFFF008    * Input port change reg (read)
+ACR    equ $FFFFF008    * Aux control reg (write)
+ISRD    equ $FFFFF00A    * interrupt status reg (read)
+IMRD    equ $FFFFF00A    * interrupt mask reg (write)
+CTU    equ $FFFFF00C    * Counter/timer upper (read)
+CTL    equ $FFFFF00E    * counter/timer lower (read)
+CTUR    equ $FFFFF00C    * Counter/timer preload upper (write)
+CTLR    equ $FFFFF00E    * counter/timer preload lower (write)
+MR1B    equ $FFFFF010    * mode reg B
+SRB    equ $FFFFF012    * status reg B
+RHRB    equ $FFFFF016    * Rx holding reg B
+IVRD    equ $FFFFF018    * interrupt vector reg
+STOPCTR    equ $FFFFF01E    * stop counter command reg (read)
+STARTCTR equ $FFFFF01C    * start counter command reg (read)
+SETOPR    equ $FFFFF01C    * bit set output register bits (write)
+CLROPR    equ $FFFFF01E    * bit clear output register (write)
+OPCR    equ $FFFFF01A    * output configuration register(write)
+</code>
+EQU template for CF interface
+<code code>
+CFdata  equ $FFFFE000       * CF data register
+CFerr   equ $FFFFE001       * CF error reg
+CFsectcnt equ $FFFFE002      * CF sector count reg
+CF07    equ $FFFFE003       * CF LA0-7
+CF815   equ $FFFFE004       * CF LA8-15
+CF1623  equ $FFFFE005       * CF LA16-23
+CF2427  equ $FFFFE006       * CF LA24-27
+CFstat  equ $FFFFE007       * CF status/command reg
+</code>