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| Both sides previous revisionPrevious revisionNext revision | Previous revision |
| builderpages:phillip_m_gallo:start [2025/01/27 11:00] – Revision from 2025-01-27 | builderpages:phillip_m_gallo:start [2026/06/15 13:04] (current) – external edit 127.0.0.1 |
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| /* Imported from Wayback Machine | /* Imported from Wayback Machine |
| Original URL : https://www.retrobrewcomputers.org/doku.php?id=builderpages:phillip_m_gallo:start | Original URL : https://retrobrewcomputers.org/doku.php?id=builderpages:phillip_m_gallo:start |
| Snapshot date: 2025-01-27 | Snapshot date: 2025-05-16 |
| Generator : wayback-archiver | Generator : wayback-archiver |
| */ | */ |
| The schematic below left is of the base kSys CPU Board. The graphic below right is the Daughter card schematic. | The schematic below left is of the base kSys CPU Board. The graphic below right is the Daughter card schematic. |
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| [[https://www.retrobrewcomputers.org/lib/exe/fetch.php?media=builderpages:phillip_m_gallo:ksys_exp_board.png|{{builderpages:phillip_m_gallo:ksys_exp_board.png?425x275|1MB Mem/RTC}}]][[https://www.retrobrewcomputers.org/lib/exe/fetch.php?media=builderpages:phillip_m_gallo:ksys_base_cpu.png|{{builderpages:phillip_m_gallo:ksys_base_cpu.png?425x275}}]]As depicts in the graphic left, the expansion hardware plugs into this board's EPROM socket. The EPROM was selected any time A15 was low. This imply's the lower 32kB of 8085 Memory Space was intended for Read Only ROM storage. As such EPROMs do not require Mem Write, Interrupt or RESET signaling. Since our expansion electronics would require this signal compliment, an addtional 2 SIP headers install to provide these necessary signals. | [[https://retrobrewcomputers.org/lib/exe/fetch.php?media=builderpages:phillip_m_gallo:ksys_exp_board.png|{{builderpages:phillip_m_gallo:ksys_exp_board.png?425x275|1MB Mem/RTC}}]][[https://retrobrewcomputers.org/lib/exe/fetch.php?media=builderpages:phillip_m_gallo:ksys_base_cpu.png|{{builderpages:phillip_m_gallo:ksys_base_cpu.png?425x275}}]]As depicts in the graphic left, the expansion hardware plugs into this board's EPROM socket. The EPROM was selected any time A15 was low. This imply's the lower 32kB of 8085 Memory Space was intended for Read Only ROM storage. As such EPROMs do not require Mem Write, Interrupt or RESET signaling. Since our expansion electronics would require this signal compliment, an addtional 2 SIP headers install to provide these necessary signals. |
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| The schematic right depicts the Expansion Board's additional 1MB of Memory (which allocates as 512kB FLASH and 512kB SRAM), as well as a Real Time Clock / Battery Supervisor (BQ4845). The CR2032 Lithium coin battery connects to the RTC/Supervisor which then routes this power to the SRAM. This way the supervisory features (power status / interrupt / Reset) can both inform and drive CPU response. | The schematic right depicts the Expansion Board's additional 1MB of Memory (which allocates as 512kB FLASH and 512kB SRAM), as well as a Real Time Clock / Battery Supervisor (BQ4845). The CR2032 Lithium coin battery connects to the RTC/Supervisor which then routes this power to the SRAM. This way the supervisory features (power status / interrupt / Reset) can both inform and drive CPU response. |
| A log of console transactions between the operator and the modified CCP can be reviewed below. | A log of console transactions between the operator and the modified CCP can be reviewed below. |
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| [[https://www.retrobrewcomputers.org/lib/exe/fetch.php?media=builderpages:phillip_m_gallo:ksys_session_log.pdf|:builderpages:phillip_m_gallo:ksys_session_log.pdf]] | [[https://retrobrewcomputers.org/lib/exe/fetch.php?media=builderpages:phillip_m_gallo:ksys_session_log.pdf|:builderpages:phillip_m_gallo:ksys_session_log.pdf]] |
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| ==== Non-Volatile Storage ==== | ==== Non-Volatile Storage ==== |
