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--- boards:sbc:sbc_v2:sbc_v2-005:development [2021/04/14 21:02] – Initial import from Wayback Machine
+++ boards:sbc:sbc_v2:sbc_v2-005:development [2026/06/15 12:00] (current) – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
+/* Imported from Wayback Machine
+   Original URL : https://retrobrewcomputers.org/doku.php?id=boards:sbc:sbc_v2:sbc_v2-005:development
+   Snapshot date: 2021-04-14
+   Generator    : wayback-archiver
+*/
+====== SBC V2-005 Development ======
+Updated design to include the following changes:
+Mb Flash memory implemented with 2 x 512Kb Flash chips.
+Dual boot ROMWBW BIOS support option.
+Expanded ROM disk option.
+Development of read/write Flash filesystem in ROMWBW
+In this development, legacy support of DIP style EPROMs and Flash chips are sacrificed for improved Flash ROM capacity. PLCC-32 style Flash chips such as the 39SF040 provide the footprint spaces saving required to mount two 512Kb chips.
+Status:
+Prototype working.
+Board routed.
+Writing 1024k rom file works.
+Board constructed.
+Testing …
+Complete
+To do:
+Test design change and prototype.
+<del>005a - Prototype did not work. Monitor CS lines identified ROM select logic does not work, so back to the drawing board.</del>
+<del>005b - Chip select logic updated. Requires additional OR gate which is unavailable. and so is implemented using discrete components.</del>
+<del>005c - Reworked chip select logic to eliminate discrete OR gate. Added 1K pullups for improved reliability.</del>
+<del>005f - Change recovery jumper to switch.</del>
+Finalize and release design.
+Speed test.
+<del>4Mhz works.</del>
+Mhz <del>flakey</del> works.
+Running daily with 12Mhz.
+Speeds as fast as 20Mhz reported working with F and AHCT parts and 55ns RAM/ROM YMMV.
+**Complete.**
+* Developing Flash4 update to support 1Mb write.
+<del>Patch developed.</del> Withdrawn, did not work. Documentation below updated.
+Flash4 Version 1.3.4 working – now in ROMWBW development build.
+**Complete.**
+Test AT49F040 compatibility
+DIP32 chips received.
+PLCC32 chips ordered.
+Both 39SF040 and 49F040 PLCC chips work with Flash4 1.3.4 and version 005c board
+**Complete.**
+Developing BIOS Flash routines.
+Chip ID working.
+Chip erase working.
+Sector erase working.
+Sector write working.
+Sector read working.
+Reading/writing to/from low memory now working,
+Flash routines integrated into memory disk drivers.
+Verify after write added.
+Testing and optimizing prior to release.
+**Complete**
+Develop bootrom flash utility for update or recovery.
+Beta version submitted to ROMWBW development build.
+**Complete**
+Dual boot ROMWBW BIOS support option.
+Canceled proposal to install jumpers to be able to boot from Flash #2.
+Utilize Xmodem Flash Updater to Flash to Flash #2
+Duplicate function added to create backup of current Flash.
+**Complete.**
+[[boards:sbc:sbc_v2:sbc_v2-005:gallery|Gallery]]
+{{[[lib:plugins:ckgedit:fckeditor:userfiles:image:boards:sbc:sbc_v2:sbc_v2-005:sbc_v2-005i.png]]
+Kicad files can be found [[https://github.com/b1ackmai1er/SBC-V2-005|here]] but may not be the most recent.
+Gerbers for sbc-v2-005i [[https://retrobrewcomputers.org/lib/exe/fetch.php?media=boards:sbc:sbc_v2:sbc_v2-005:sbc_v2-005i-gerbers.zip|here.]]
+====== Flash Programming ======
+Will Sowerbutts has updated his FLASH4 program to support programming one or more flash devices.
+To assemble a 1024Kb ROMWBW rom, use the following as an example command line: ''%%buildrom SBC std 1024%%''
+Example output below shows and existing 1024Kb Flash system setup with a 512Kb BIOS being reflashed to a 1024Kb BIOS.
+<code code>
+RomWBW HBIOS v3.1.1-pre.22, 2020-10-26
+SBC Z80 @ 10.000MHz
+MEM W/S, 1 I/O W/S, INT MODE 2
+KB ROM, 512KB RAM
+...
+CP/M-80 v2.2, 54.0K TPA
+B>h:crc b:*.*
+CRC:  File CRC Check Utility  v1.1
+ASM      COM CBA8 | CLRDIR   COM 7843 | COMPARE  COM 4938 | COPY     CFG C718
+COPY     COM ADB0 | DDT      COM AA45 | DDTZ     COM FC4B | DUMP     COM 3CE0
+ED       COM 7D38 | FA16     CFG E248 | FDISK80  COM 363D | FILEATTR COM 8A5C
+FILEDATE CFG F929 | FILEDATE COM 7C71 | FLASH    COM 5653 | INITDIR  CFG 8768
+INITDIR  COM DA1C | LDDS     COM 1F44 | LDP2D    COM 7517 | LINK     COM F122
+LOAD     COM 2A62 | MBASIC   COM B29D | NULU     COM 10DF | PIP      COM B75C
+PUTDS    COM 35D0 | RELOG    COM 8B9F | RMAC     COM 5077 | STAT     COM 4CED
+SUBMIT   COM DE5C | SUPERSUB COM F3D0 | TD       CFG 56F0 | TD       COM C435
+UNARC    COM 8A9D | XSUB     COM E86D | ZAP      COM 7D48 | ZCAL     COM 7373
+ZCNFG    COM 27F3 | ZCNFG24  CFG F662 | ZDE      COM 5017 | ZPATH    COM 1236
+ZSCONFIG COM 7853 | ZXD      CFG B7AC | ZXD      COM AF1C | ASSIGN   COM 696F
+FDU      COM 72FB | FORMAT   COM C2C0 | MODE     COM 2801 | RTC      COM 4721
+SURVEY   COM C209 | SYSCOPY  COM C510 | SYSGEN   COM 332B | TALK     COM B866
+TIMER    COM 111D | XM       COM 9EAC | INTTEST  COM 9231 | CPM      SYS 75D8
+ZSYS     SYS C70D
+Sum of Listed CRCs = 6D17
+H>flash write SBC_std.rom /2
+FLASH4 by Will Sowerbutts <will@sowerbutts.com> version 1.3.4
+Using RomWBW (v2.6 ) bank switching.
+Flash memory chip ID is 0xBFB7: 39F040 (512KB)
+Flash memory has 2 chips, each 128 sectors of 4096 bytes, total 1024KB
+Write complete: Reprogrammed 224/256 sectors.
+Verify (256 sectors) complete: OK!
+reboot ...
+RomWBW HBIOS v3.1.1-pre.22, 2020-10-27
+SBC Z80 @ 9.996MHz
+MEM W/S, 1 I/O W/S, INT MODE 2
+KB ROM, 512KB RAM
+...
+B>h:crc b:*.*
+CRC:  File CRC Check Utility  v1.1
+ASM      COM CBA8 | CLOCKS   DAT AFB3 | CLRDIR   COM 7843 | COMPARE  COM 4938
+COPY     CFG C718 | COPY     COM ADB0 | COPY     UPD 5602 | CR       COM EE12
+DATSWEEP COM 22FA | DDT      COM AA45 | DDTZ     COM FC4B | DDTZ     DOC 8DAC
+DIRX     COM E275 | DSCONFIG COM DA79 | DUMP     COM 3CE0 | ED       COM 7D38
+FA16     CFG E248 | FA16     DOC D9DD | FA16A    FOR 0153 | FA16CFG  TXT E37E
+FAT      COM B5B3 | FDISK80  COM 363D | FILEATTR COM 8A5C | FILEDATE CFG F929
+FILEDATE COM 7C71 | FLASH    COM 5653 | INITDIR  CFG 8768 | INITDIR  COM DA1C
+LBREXT   COM 3AB9 | LDDS     COM 1F44 | LDNZT    COM F03D | LDP2D    COM 7517
+LIB      COM 7224 | LINK     COM F122 | LOAD     COM 2A62 | MAC      COM 8E10
+MBASIC   COM B29D | NULU     COM 10DF | PIP      COM B75C | PMARC    COM A94D
+PMEXT    COM 8A89 | PUTBG    COM 80F2 | PUTDS    COM 35D0 | RELOG    COM 8B9F
+RMAC     COM 5077 | SETTERM  COM 5899 | SETUPZST COM 3AF8 | STAMPS   DAT CB63
+STAT     COM 4CED | SUBMIT   COM DE5C | SUPERSUB COM F3D0 | TD       CFG 56F0
+TD       COM C435 | TERMBASE DAT B083 | TESTCLOK COM 5641 | UNARC    COM 8A9D
+UNCR     COM A32E | UNZIP    COM 86B3 | XSUB     COM E86D | ZAP      COM 7D48
+ZCAL     COM 7373 | ZCNFG    COM 27F3 | ZCNFG24  CFG F662 | ZDE      COM 5017
+ZDENST   COM 8D20 | ZPATH    COM 1236 | ZSCONFIG COM 7853 | ZSID     COM 08D7
+ZSVSTAMP COM 4FC4 | ZSVSTAMP DOC 4CB4 | ZXD      CFG B7AC | ZXD      COM AF1C
+ASSIGN   COM 696F | FDU      COM 72FB | FORMAT   COM C2C0 | MODE     COM 2801
+RTC      COM 4721 | SURVEY   COM C209 | SYSCOPY  COM C510 | SYSGEN   COM 332B
+TALK     COM B866 | TIMER    COM 111D | XM       COM 9EAC | INTTEST  COM 9231
+CPM      SYS 75D8 | ZSYS     SYS C70D
+Sum of Listed CRCs = E4CD
+</code>
+The updated Flash4 can be found in Will Sowerbutts github repository https://github.com/willsowerbutts/flash4
+====== 39SF040 programming on the SBC-V2 ======
+Programming is complicated by the memory banking scheme and the critical aspect is that the sector erase and byte program addresses need to be read or written in conjunction with the bank select lines.
+[[https://www.retrobrewcomputers.org/lib/exe/fetch.php?tok=2f1912&media=https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/boards/sbc/sbc_v2/sbc_v2-005/mapping.png|{{https://www.retrobrewcomputers.org/lib/plugins/ckgedit/fckeditor/userfiles/image/boards/sbc/sbc_v2/sbc_v2-005/mapping.png?800x288}}]]
+The following routines have been developed to access 39SF040 Flash devices in the ROMWBW environment:
+Identify Flash Chip
+Erase Flash Sector
+Read Flash Sector
+Verify Flash Sector
+Write Flash Sector
+These are relocatable routines as they must be executed from the high memory area (>8000h) as Flash and RAM is switched in and out of the low memory area (<8000h).
+When these routines are required to be access by BIOS drivers, individual routines are copied to a high memory buffer before execution on an as needed basis.
+When the routines are being used by an application then all routines can be relocated to high memory and remain there.
+====== Circuit Description ======
+The SBC-V2 already supports up to 1Mb of EPROM. However, the maximum DIP-32 style Flash device is 512Kb as Flash requires a write pin, so it has one less address line.
+Two chip select signals need to be developed to cater for the change from a 1Mb device to 2x512Kb devices This is achieved using the existing chip select signal /CS_ROM and the A19 address line.
+When /CS_ROM is active (low), A19 determines which chip is selected. The required logic table is:
+<code code>
+/CS_ROM A19 /CS_ROM1 /CS_ROM2
+     1      1       1
+     0      1       1
+     1      1       0
+     0      0       1
+</code>
+Note that when /CS_ROM is high, neither flash chip is active.
+The ideal logic elements to develop these signals are shown in Figure 1 below. However, the SBC-V2 does not have a spare OR gate so a discrete component OR gate was implemented initially. This required adding two diodes and a resistor to the board layout.
+An OR gate can also be replaced by a NAND gate with both inputs inverted as shown in Figure 2. However, the SBC-V2 only has two spare inverters.
+The final design is implemented in Figure 3 which uses the remaining spare components on the SBC-V2 board.
+{{[[lib:plugins:ckgedit:fckeditor:userfiles:image:boards:sbc:sbc_v2:sbc_v2-005:sbc_v2-005-logic.png]]
+====== Flash Filesystem ======
+Status
+ROMWBW recognizes type of Flash chips installed.
+HBIOS disables Flash file system driver if 39F040 chips are not installed.
+First read and write to CP/M flash drive achieved.
+Beta memory disk driver update submitted to ROMWBW development build.
+{{[[lib:plugins:ckgedit:fckeditor:userfiles:image:boards:sbc:sbc_v2:sbc_v2-005:flashfs.png]]
+To enable the flash file system add the following to your configuration file
+<code code>
+MDFFENABLE   .SET  TRUE   ; MD: ENABLE FLASH FILE SYSTEM
+</code>
+Then rebuild and update your existing flash BIOS as described under [[boards:sbc:sbc_v2:sbc_v2-005|Boot ROM Installation]] and [[boards:sbc:sbc_v2:sbc_v2-005|Flash Programming]].
+====== Xmodem Flash Updater ======
+The Flash updater allows the ROMWBW BIOS to be upgraded via xmodem file transfer.
+The Flash chip is programmed during the file transfer, avoiding the need for secondary storage to hold the ROM file.
+As such as 128Mb *.upd system update file or a full 512Kb or 1024Kb *.rom image file can be written to the Flash memory without a secondary storage device.
+{{[[lib:plugins:ckgedit:fckeditor:userfiles:image:boards:sbc:sbc_v2:sbc_v2-005:updater.png]]
+The updater also has the facility to copy the contents of Flash #1 to Flash #2 in order to create a backup.
+The Xmodem Flash Updater is supplied as a User ROM. To install, overwrite the current userrom.asm stub file with the updater.asm file. Then rebuild and update your existing flash BIOS as described under [[boards:sbc:sbc_v2:sbc_v2-005|Boot ROM Installation]] and [[boards:sbc:sbc_v2:sbc_v2-005|Flash Programming]].
+An 8Mhz or faster CPU clock is required to keep up with the default 38400 baud rate. Clock speeds as low as 2Mhz can be used if the baud rate is lowered to 9600 baud. The development build of ROMWBW has been extended to allow baud rates to be changed from the boot menu using the //Set Console Interface// option.
+<code code>
+  I <u> [<c>] - Set Console Interface/Baud code
+</code>
+Example: To change current console to 9600 baud
+<code code>
+I 0 13
+</code>
+Baud rate codes are:
+[[boards:sbc:sbc_v2:sbc_v2-005:development|{{https://retrobrewcomputers.org/lib/exe/fetch.php?media=boards:sbc:sbc_v2:sbc_v2-005:83c9a7bb595c6ae9c686ae8b2e1ad2cd.png}}]]