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--- boards:sbc:ns32000 [2025/04/28 03:49] – Revision from 2025-04-28
+++ boards:sbc:ns32000 [2026/06/15 12:53] (current) – external edit 127.0.0.1
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+/* Imported from Wayback Machine
+   Original URL : https://retrobrewcomputers.org/doku.php?id=boards:sbc:ns32000
+   Snapshot date: 2025-01-15
+   Generator    : wayback-archiver
+*/
+====== National Semiconductor 32000 ======
+The introduction of the NS16032, quickly renamed NS32016, followed the introduction by Intel of the 8086 and the introduction by Motorola of the MC68000. All three chips used a 16-bit external bus, but internally the 68000 and 32016 were fully 32-bit computers. Just as the Intel 8086 led to a whole series of chips (80286, 80386, …); the Motorola 68000 led to a whole series of chips (68010, 68020, 68030, …); likewise, the National Semiconductor 32016 led to a series of chips (32032, 32332, 32532).
+Unfortunately, the National chips were never as big a commercial success as the Intel and Motorola offerings. National did find a market in a series of chips as embedded controllers in peripheral devices.
+New to the 32000 was the “module” architecture. Motorola started down this route with the 68020, but abandoned the idea with the 68030 and later chips. National kept the architecture through its entire upgraded line, 32332, 32532, and into the controller chips 32CG16, 32CG160, 32FG16, and so on.
+Here is a link to one of the best sites paying tribute to the NS32000: [[http://www.cpu-ns32k.net/index.html|http:%%//%%www.cpu-ns32k.net]]
+Here is a link to my S-100 board built many years ago using the NS32016 chipset: http://www.cpu-ns32k.net/John.html
+===== RetroBrew project =====
+With some interest shown with my inquiry about the NS32000 series on the Forum, the criteria for any board was
+NS32CG160 over NS32CG16
+Mb SRAM
+UART
+U size
+The FPU was desired, but board size didn't permit it. That is, until the following compromises were made.
+SRAM is surface mount. The SSOP and TSOP II packages have 50mil pin centers. Not too bad to solder. A custom footprint on the board allows either package to be used (they are different widths).
+ROM is reduced to 8-bit width. This required upgrading a 74LS245 to 74LS646 (20-pin to 24-pin), and adding a 20-pin GAL to control access.
+The NS32181 FPU now fits (snugly).
+{{[[lib:plugins:ckgedit:fckeditor:userfiles:image:boards:sbc:ns32cg160_1-0_components.png]]
+This board is a fully stand-alone Single Board Computer with:
+RTC and NVRAM using the familiar DS1302 chip.
+-bit IDE interface connected to the DMA controller. Software will be PIO or DMA, whichever works.
+The RetroBrew bus connector, DIN 41612 is entirely optional. Power may be supplied through the Molex connector.
+Jumper selectable wait states for ROM, external memory, and I/O. SRAM is wired at 0 wait states.
+Blinken lights: User/Supversor state; HALT (wait for interrupt) condition.
+**THIS BOARD IS <del>HIGHLY EXPERIMENTAL</del>** **OPERATIONAL** at this time. As of 6/1/2020, the above prototype is passing all its checkout tests. A rev. 2.0 board now exists to incorporate the rev. 1.0 errata (12/1/2020).
+===== CPU References and Development Software =====
+There is no target OS for this board at this time. I am highly open to suggestions.
+Here are the [[https://retrobrewcomputers.org/lib/exe/fetch.php?media=boards:sbc:ns32cg160-25.pdf|NS32CG160 CPU]] and [[https://retrobrewcomputers.org/lib/exe/fetch.php?media=boards:sbc:ns32181.pdf|NS32181 FPU]] hardware datasheets.
+The [[https://retrobrewcomputers.org/lib/exe/fetch.php?media=boards:sbc:ns32cg160_instruction_set_manual.pdf|NS32CG160 Instruction Set]] manual is an edited version of the full '532: [[https://retrobrewcomputers.org/lib/exe/fetch.php?media=boards:sbc:ns32000_instruction_set_manual_2017.pdf|NS32000 Instruction Set]] manual. The '532 manual has MMU, Custom Slave instructions, as well as extra CPU & Debug registers.
+The best development suite I have seen is the [[https://retrobrewcomputers.org/lib/exe/fetch.php?media=boards:sbc:ns32k-gcc-3.4.6.tar.bz2|GCC 3.4.6]] compiler //and// //utilities// for '532 NetBSD. It runs on 64-bit Linux.
+[14-May-2020]
+===== CPU References and Development Software =====
+There is no target OS for this board at this time. I am highly open to suggestions.
+Here are the [[https://retrobrewcomputers.org/lib/exe/fetch.php?media=boards:sbc:ns32cg160-25.pdf|NS32CG160 CPU]] and [[https://retrobrewcomputers.org/lib/exe/fetch.php?media=boards:sbc:ns32181.pdf|NS32181 FPU]] hardware datasheets.
+The [[https://retrobrewcomputers.org/lib/exe/fetch.php?media=boards:sbc:ns32cg160_instruction_set_manual.pdf|NS32CG160 Instruction Set]] manual is an edited version of the full '532: [[https://retrobrewcomputers.org/lib/exe/fetch.php?media=boards:sbc:ns32000_instruction_set_manual_2017.pdf|NS32000 Instruction Set]] manual. The '532 manual has MMU, Custom Slave instructions, as well as extra CPU & Debug registers.
+The best development suite I have seen is the [[https://retrobrewcomputers.org/lib/exe/fetch.php?media=boards:sbc:ns32k-gcc-3.4.6.tar.bz2|GCC 3.4.6]] compiler //and// //utilities// for '532 NetBSD. It runs on 64-bit Linux.
+[14-May-2020]
+===== NS32016 / NS32532 / NS32CG160 CPU Differences Noted =====
+The NS32CG160 board does not support the SETCFG instruction. Instead, the configuration register is read/written with the LPRD cfg instruction.
+Unlike the NS32532, the 'CG160 does not have processor registers DCR, BPC, DSR, or CAR debug registers.
+There either is no assembler support for the UPSR or USP registers as directly accessible in supervisor state. The SP registers may be diddled by toggling the S bit in the PSR in supervisor state, and the User PSR may be diddled during a RETT or RETI instruction.
+The 'CG160 has all the OEM peripherals: DMA & Timers.
+Interrupts are totally different on the 'CG160. No NS32202 chip is usable.
+The 'CG160 has a DE (Direct Exception) bit in the Configuration Register. This bit defeats the Module calling during interrupts and traps. The NetBSD compiler doesn't support the module capability, anyhow.
+The 'CG160 has no MMU or CustomCoprocessor capability. The C & M bits in the configuration register instead control division of the input oscillator clock by 2, 4, 8 for power saving.
+It is a shame this chip has only 24 address lines.