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| + | /* Imported from Wayback Machine | ||
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| + | */ | ||
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| + | ====== Multicomp Papilio Duo (Xilinx Spartan-6) ====== | ||
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| + | Portions of the hardware and designs on this page are based on Grant Searle' | ||
| + | “By downloading these files you must agree to the following: The original copyright owners of ROM contents are respectfully acknowledged. Use of the contents of any file within your own projects is permitted freely, but any publishing of material containing whole or part of any file distributed here, or derived from the work that I have done here will contain an acknowledgement back to myself, Grant Searle, and a link back to this page. Any file published or distributed that contains all or part of any file from this page must be made available free of charge.” -http:// | ||
| + | |||
| + | ===== Introduction ===== | ||
| + | |||
| + | Welcome to my recently completed Project using the awesome **Papilio Duo platform with the Classic Computing Shield (Xilinx** **Spartan** **6).** It's a migration of **Grant Searle' | ||
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| + | I've built the **Z80 CP/M variant**, complete with VGA & Keyboard terminal, Serial port, SD-Card and external SRAM. The steps I followed to accomplish this: | ||
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| + | 1. Adapted the pinouts, ports and some signals of all the modules (Main Interconect, | ||
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| + | 2. Converted the original 6 bit color VGA to 12 bit color interface. | ||
| + | |||
| + | 2. Converted the internal BIOS ROM and Character Font ROMs, to use Xilinx' | ||
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| + | 3. Converted the internal double port Display & Attribute RAMs also to use the Core Generator' | ||
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| + | 4. In my first attempt I adapter the CPU and Baudrate clock generators, to use the Papilio' | ||
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| + | Wherever possible I tried to maintain Grant' | ||
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| + | The final outcome is a very usable and complete Z80 soft-core based machine, running Digital Research CP/M 2.2 OS. The modular design concept allows for extensive hacks and mods. | ||
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| + | Hope you enjoy it ! | ||
| + | |||
| + | ===== Hardware & FPGA Bitstream Documentation ===== | ||
| + | |||
| + | ===== Build Information ===== | ||
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| + | I've attached some pictures of my working system and the full VHDL ISE 14.7 Project tree files, including an already generated “bit” file for transferring it to the Papilio Duo with the Computing Shield attached (default serial port baudrate is 9600, 8N1 no handshake). | ||
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| + | I've also included a ready to go SD card image (SD only, not SDHC for now, 1 or 2 GB) with all the CP/M partitioning work already done including a very comprehensive software collection courtesy of Oscar Vermeulen (drives A to D, Users 0 to 9). | ||
| + | |||
| + | **Link to Project files:** | ||
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| + | https:// | ||
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| + | **Link to SD Card image with CP/M 2.2 Software Collection: | ||
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| + | https:// | ||
| + | |||
| + | ===== Builder' | ||
| + | |||
| + | Please use this space to add any notes/ | ||
| + | |||
| + | ===== Photo Gallery ===== | ||
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| + | [[boards: | ||
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| + | [[boards: | ||
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| + | [[boards: | ||
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| + | [[boards: | ||
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| + | \\ | ||
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| + | ===== File List ===== | ||
| + | |||
| + | Filename | ||
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| + | Filesize | ||
| + | Last modified | ||
| + | [[https:// | ||
| + | 194.6 MiB | ||
| + | 2016/09/19 22:50 | ||
| + | [[https:// | ||
| + | 24.5 MiB | ||
| + | 2016/09/15 17:57 | ||
