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| boards:ecb:dskyng [2025/01/04 01:03] – Revision from 2025-01-04 | boards:ecb:dskyng [2026/06/15 12:50] (current) – external edit 127.0.0.1 | ||
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| + | /* Imported from Wayback Machine | ||
| + | | ||
| + | | ||
| + | | ||
| + | */ | ||
| + | |||
| + | ====== Next Generation Display & Keyboard (DSKYng) ====== | ||
| + | |||
| + | {{[[lib: | ||
| + | |||
| + | ===== Introduction ===== | ||
| + | |||
| + | The DSKYng provides a low-level interface to the hardware on the RBC Z80 SBC (and others). This Intel 8279 based display and keyboard provides a simple to program buffered keyboard and display for simple tasks. It is supported by the monitor in RomWBW allowing the user can inspect/ | ||
| + | |||
| + | Special thanks to Andrew Lynch, Wayne Warthen, and John Coffman for their assistance with the design, development and testing of the DSKYng. | ||
| + | |||
| + | ===== Hardware Documentation ===== | ||
| + | |||
| + | |BOARD | ||
| + | |SCHEMATIC | ||
| + | |GERBERS | ||
| + | |KICAD SOURCE|[[https:// | ||
| + | |||
| + | The DSKYng provides two pass-through interfaces. The “IO” port is compatible with the original and V2 SBC parallel port and the “PPIDE” port is compatible with a PPIDE based port such as the one on the new SBC. Note that these cannot be used at the same time and are provided only to allow compatibility to as many of the SBC configurations as possible. Note that the DSKYng is compatible with an IDE based HDD or CF card running on the PPIDE bus or IO bus. | ||
| + | |||
| + | Power can be provided to the DSKYng through either the: | ||
| + | |||
| + | * PPIDE bus (jumper J9 Shorted) | ||
| + | |||
| + | * IO Bus (Jumper J1 1&2 Shorted) | ||
| + | |||
| + | * Directly with regulated 5v (Jumper J1, apply power to pins 2 & 3) | ||
| + | |||
| + | * Directly with unregulated 7-9V (unregulated power connector . . requires optional power regulator components) | ||
| + | |||
| + | When Attaching to the IO port Jumpers J10&11 need to be open, Jumper J5 needs to be jumpered to pins 2&3 and any software needs to be configured for an “Active Low” reset signal. | ||
| + | |||
| + | When Attaching to the PPIDE port Jumpers J10&11 need to be shorted, Jumper J5 needs to be jumpered to pins 1&2 and any software needs to be configured for an “Active High” reset signal. | ||
| + | |||
| + | ===== Build Information ===== | ||
| + | |||
| + | ==== Parts List ==== | ||
| + | |||
| + | ^ID ^Quantity^Part Number | ||
| + | |C1-9 |9 | ||
| + | |C10 | ||
| + | |C11 | ||
| + | |D1-24 | ||
| + | |J1 |1 | ||
| + | |J2 |1 | ||
| + | |J3-4 |2 | ||
| + | |J5 |1 | ||
| + | |J6 |1 | ||
| + | |J7-8 |2 | ||
| + | |J9 |1 | ||
| + | |Q1-6, | ||
| + | |Q7-10, | ||
| + | |R1 |1 |10K Resistor | ||
| + | |R2, | ||
| + | |R3-8, | ||
| + | |SW1-30 | ||
| + | |U1, | ||
| + | |U2 |1 | ||
| + | |U3, | ||
| + | |U4 |1 | ||
| + | |U7-U16 | ||
| + | |U15 | ||
| + | |U17 | ||
| + | |X1 |1 | ||
| + | |BZ1 | ||
| + | |||
| + | *(a buzzer such as the one here [[https:// | ||
| + | |||
| + | ==== Keycap Sourcing Notes ==== | ||
| + | |||
| + | Because the key are not in a “normal” keyboard arrangement, | ||
| + | |||
| + | Reasonable priced SA (almost uniform) profile shine-through key caps: https:// | ||
| + | |||
| + | low cost standard profile keys can be found here: [[https:// | ||
| + | |||
| + | low cost translucent keys can be found here, BUT these are not pre-printed: | ||
| + | |||
| + | ===== Software Documentation ===== | ||
| + | |||
| + | Example code for using the DSKYng can be referenced from the RomWBW repo. Specifically / | ||
| + | |||
| + | <code code> | ||
| + | ; LED SEGMENTS (BIT VALUES) | ||
| + | ; | ||
| + | ; | ||
| + | ; | ||
| + | ; | ||
| + | ; | ||
| + | ; | ||
| + | ; | ||
| + | |||
| + | ; KEY CODE MAP (KEY CODES) --CCCRRR | ||
| + | ; | ||
| + | ; | ||
| + | ; | ||
| + | ; | ||
| + | ; | ||
| + | ; | ||
| + | ; | ||
| + | ; | ||
| + | ; LED BIT MAP (BIT VALUES) | ||
| + | ; | ||
| + | ; $08 $09 $0A $0B $0C $0D $0E $0F | ||
| + | ; --- --- --- --- --- --- --- --- | ||
| + | ; 01 | ||
| + | ; 02 | ||
| + | ; 04 | ||
| + | ; 08 | ||
| + | ; 10 | ||
| + | ; 20 | ||
| + | ; | ||
| + | |||
| + | PPIA .EQU DSKYPPIBASE + 0 ; PORT A | ||
| + | PPIB .EQU DSKYPPIBASE + 1 ; PORT B | ||
| + | PPIC .EQU DSKYPPIBASE + 2 ; PORT C | ||
| + | PPIX .EQU DSKYPPIBASE + 3 ; PPI CONTROL PORT | ||
| + | ; | ||
| + | |||
| + | DSKY_PPIX_RD: | ||
| + | DSKY_PPIX_WR: | ||
| + | ; | ||
| + | ; PIO CHANNEL C: | ||
| + | ; | ||
| + | ; | ||
| + | ; | ||
| + | ; | ||
| + | |||
| + | ; SETTING BITS 3 & 4 WILL ASSERT /CS ON 3279 | ||
| + | ; CLEAR BITS 1 OR 2 TO ASSERT READ/WRITE | ||
| + | ; | ||
| + | |||
| + | DSKY_PPI_IDLE: | ||
| + | ; | ||
| + | DSKY_CMD_CLR: | ||
| + | DSKY_CMD_CLRX: | ||
| + | DSKY_CMD_WDSP: | ||
| + | DSKY_CMD_RDSP: | ||
| + | DSKY_CMD_CLK: | ||
| + | DSKY_CMD_FIFO: | ||
| + | ; | ||
| + | |||
| + | DSKY_PRESCL: | ||
| + | </ | ||
| + | |||
| + | [[https:// | ||
