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boards:ecb:diskio-v3:start [2019/07/21 16:28] – Initial import from Wayback Machine boards:ecb:diskio-v3:start [2026/06/15 12:20] (current) – external edit 127.0.0.1
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 /* Imported from Wayback Machine /* Imported from Wayback Machine
    Original URL : https://retrobrewcomputers.org/doku.php?id=boards:ecb:diskio-v3:start    Original URL : https://retrobrewcomputers.org/doku.php?id=boards:ecb:diskio-v3:start
-   Snapshot date: 2019-07-21+   Snapshot date: 2025-11-17
    Generator    : wayback-archiver    Generator    : wayback-archiver
 */ */
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 //IDE Support:// //IDE Support://
  
-The DISK IO V3 board implements the IDE interface via PPIDE. So, in your custom build config file you want:+The DISK IO V3 board implements the IDE interface via PPIDE. PPIDE is supported in ROMWBW but is not enabled by default. Up to three IDE interfaces can be used and when enabled ROMWBW will look for them on port 60h, 20h and 44h respectively. 
 + 
 +To enable IDE support and set the number of interfaces available, update your custom configuration: 
 + 
 +SBC_std_cust.asm
  
 <code code> <code code>
 PPIDEENABLE    .SET    TRUE              ; TRUE FOR PPIDE DEVICE SUPPORT PPIDEENABLE    .SET    TRUE              ; TRUE FOR PPIDE DEVICE SUPPORT
-PPIDEMODE      .SET    PPIDEMODE_DIO3    ; PPIDEMODE_SBC, PPIDEMODE_DIO3, PPIDEMODE_MFP+PPIDECNT       .SET    1                 ; NUMBER OF 8255 CHIPS. EACH WILL SUPPORT TWO DRIVES 
 +</code> 
 + 
 +Further customization of ports and IDE modes done by adding and changing these definitions in your customer configuration file. 
 + 
 +<code code> 
 +PPIDE0BASE     .SET    $60          ; PPIDE 0: PPI REGISTERS BASE ADR 
 +PPIDE0A8BIT    .SET    FALSE        ; PPIDE 0A (MASTER): 8 BIT XFER 
 +PPIDE0B8BIT    .SET    FALSE        ; PPIDE 0B (SLAVE): 8 BIT XFER 
 +PPIDE1BASE     .SET    $20          ; PPIDE 1: PPI REGISTERS BASE ADR 
 +PPIDE1A8BIT    .SET    FALSE        ; PPIDE 1A (MASTER): 8 BIT XFER 
 +PPIDE1B8BIT    .SET    FALSE        ; PPIDE 0B (SLAVE): 8 BIT XFER 
 +PPIDE2BASE     .SET    $44          ; PPIDE 2: PPI REGISTERS BASE ADR 
 +PPIDE2A8BIT    .SET    FALSE        ; PPIDE 2A (MASTER): 8 BIT XFER 
 +PPIDE2B8BIT    .SET    FALSE        PPIDE 0B (SLAVE): 8 BIT XFER
 </code> </code>
  
-Make sure that IDEENABLE is set back to false:+Make sure that IDEENABLE is set back to false unless you have another device with has a true IDE interface:
  
 <code code> <code code>
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